Jurnal IJERA: General Algorithm For Testing The Combinational Logic Gates Inside Digital Integrated Circuits
NIP Peneliti
197711202005011002
Nama Peneliti
Sidik Nurcahyo, S.T., M.T.
Kategori
JURNAL
Judul
Jurnal IJERA: General Algorithm for Testing the Combinational Logic Gates Inside Digital Integrated Circuits
Alamat Jurnal (Halaman ini)
https://simpeg.polinema.ac.id/peer_review/data/jurnal/2017/jurnal-ijera--general-algorithm-for-testing-the-combinational-logic-gates-inside-digital-integrated-circuits
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